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ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor features ar0237cs/d rev. 4, 6/16 en 1 ?semiconductor components industries, llc 2016, 1/2.7-inch 2.1 mp/full hd digital image sensor ar0237/d, rev. 4 for the latest datasheet, please visit www.onsemi.com features ? superior low-light performance ? latest 3.0 ? m pixel with on semiconductor dr-pix? technology with dual conversion gain ? full hd support at up to 1080p 60 fps for superior video performance ? linear or high dynamic range capture ? supports line interleaved t1/t2 readout to enable hdr processing in isp chip ? support for external mechanical shutter ? on-chip phase-locked loop (pll) oscillator ? integrated position-based color and lens shading correction ? slave mode for precise frame-rate control ? stereo/3d camera support ? statistics engine ? data interfaces: four-lane serial high-speed pixel interface (hispi) differential signaling (slvs and hiv cm ), or parallel ? auto black level calibration ? high-speed configurable context switching ? temperature sensor applications ? video surveillance ? 1080p60 (surveillance) video applications ? high dynamic range imaging general description on semiconductor's ar0237 is a 1/2.7-inch cmos digital image sensor with an active-pixel array of 1928hx1088v. it captures ima ges in either linear or high dynamic range modes, with a rolling-shutter readout. it includes soph isticated camera functions such as in-pixel binning, windowing and both video and single frame modes. it is designed for both low light and high dynamic range scene performance. it is programmable through a simp le two-wire serial inter- face. the ar0237 produces extraordinarily clear, sharp digital pictures, and its ability to capture both continu- ous video and single frames makes it the perfect choice for a wide range of applications, including surveillance and hd video. table 1: key parameters parameter typical value optical format 1/2.7-inch (6.6 mm) active pixels 1928(h) x 1088(v) (16:9 mode) pixel size 3.0 ? m x 3.0 ?? m color filter array rgb bayer, rgb-ir shutter type electronic rolling shutter and grr input clock range 6 C 48 mhz output clock maximum 148.5 mp/s (4-lane hispi) 74.25 mp/s (parallel) output serial hispi 10-, 12-, 14-, 16-, or 20-bit parallel 10-, 12-bit frame rate 1080p 60 fps linear hispi 30 fps linear parallel 30 fps line interleaved hispi 15 fps line interleaved parallel responsivity 4.0 v/lux-sec snr max 41 db max dynamic range up to 96 db supply voltage i/o 1.8 or 2.8 v digital 1.8 v analog 2.8 v hispi 0.3 v - 0.6 v (slvs), 1.7 v - 1.9 v (hivcm) power consumption (typical) < 300mw line interleaved 1080p30 <190mw 1080p30 linear mode operating temperature C30c to +85c ambient package options 10x10 mm 80-pin ibga 11.43x11.43 mm 48-pin mplcc
ar0237cs/d rev. 4, 6/16 en 2 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor ordering information ordering information see the on semiconductor device nomenclature document (tnd310/d) for a full description of the naming convention used for image sensors. fo r reference documenta- tion, including information on evaluation kits, please visi t our web site at www.onsemi.com. table 2: available part numbers part number product description orderable product at tribute description AR0237CSSC00SUEA0-DR 2mp 1/2.7" image sensor, rgb, 0 deg cra, ibga package, multi output drypack ar0237cssc00shra0-dr 2mp 1/2.7" image sensor, rgb, 0 deg cra, mplcc package, hispi output drypack ar0237cssc00spra0-dr 2mp 1/2.7" image sensor, rgb, 0 deg cra, mplcc package, parallel output drypack ar0237cssc12shra0-dr 2mp 1/2.7" image sensor, rgb, 12 deg cra, mplcc package, hispi output drypack ar0237cssc12spra0-dr 2mp 1/2.7" image sensor, rgb, 12 deg cra, mplcc package, parallel output drypack ar0237irsh12shra0-dr-e 2mp 1/2.7" image sensor, rgb-ir, 12 deg cra, mplcc package, hispi output drypack ar0237irsh12spra0-dr-e 2mp 1/2.7" image sensor, rgb-ir, 12 deg cra, mplcc package, parallel output drypack ar0237cssc00sueah3-gevb rgb, 0 deg cra, ibga package, multi output, headboard headboard ar0237cssc00shrah3-gevb rgb, 0 deg cra, mplcc package, hispi output, headboard headboard ar0237cssc00sprah3-gevb rgb, 0 deg cra, mplcc package, parallel output, headboard headboard ar0237cssc12shrah3-gevb rgb, 12 deg cra, mplcc package, hispi output, headboard headboard ar0237cssc12sprah3-gevb rgb, 12 deg cra, mplcc package, parallel output, headboard headboard ar0237irsh12shrah3-gevb rgb-ir, 12 deg cra, mplcc package, hispi output, headboard headboard ar0237irsh12sprah3-gevb rgb-ir, 12 deg cra, mplcc package, parallel output, headboard headboard
ar0237cs/d rev. 4, 6/16 en 3 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor ordering information
ar0237cs/d rev. 4, 6/16 en 4 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 functional overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 pixel data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 features overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 power-on reset and standby timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
ar0237cs/d rev. 4, 6/16 en 5 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor general description general description the on semiconductor ar0237 can be operated in its default mode or programmed for frame size, exposure, gain, and other parame ters. the default mode output is a 1080p- resolution image at 60 frames per second (fps) through th e hispi port. in linear mode, it outputs 12-bit or 10-bit a-law compressed raw data, using either the parallel or serial (hispi) output ports. in high dynamic range mode, it outputs two exposure values that the isp will combine into an hdr image. the device may be operated in video (master) mode or in single frame trigger mode. frame_valid and line_valid signals are ou tput on dedicated pins, along with a synchronized pixel clock in parallel mode. the ar0237 includes additional features to allow application-specific tuning: windowing and offset, auto black level corr ection, and on-board temperature sensor. optional register information and histogra m statistic information can be embedded in the first and last 2 lines of the image frame. the ar0237 is designed to operate over a wide temperature range of -30c to +85c ambient.
ar0237cs/d rev. 4, 6/16 en 6 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor functional overview functional overview the ar0237 is a progressive-scan sensor that generates a stream of pixel data at a constant frame rate. it uses an on-chip, phas e-locked loop (pll) that can be optionally enabled to generate all internal clocks from a single master input clock running between 6 and 48 mhz. the maximum output pixel rate is 148.5 mp/s, corresponding to a clock rate of 74.25 mhz. figure 1 shows a block diag ram of the sensor configured in linear mode, and in hdr mode. figure 1: block diagram of ar0237 user interaction with the sensor is throug h the two-wire serial bus, which communi- cates with the array control, analog signal chai n, and digital signal chain. the core of the sensor is a 2.1 mp active- pi xel sensor array. the timing and control circuitry sequences through the rows of the array, resetting and then reading each row in turn. in the time interval between resetting a row and reading that row, the pixels in the row integrate incident light. the exposure is controlled by varying the time interval between reset and readout. once a row has been read, the data from the columns is sequenced through an analog signal chain (providing offset correct ion and gain), and then through an analog- to-digital converter (adc). the output from the adc is a 12-bit value for each pixel in the array. the adc output passes through a digital processing signal chain (which provides further data path corrections and appl ies digital gain). the sensor also offers a row noise correction black level correction test pattern generator pixel defect correction digital gain and pedestal a-law compression parallel hispi 12 bits 10 bits 12 12 adc data
ar0237cs/d rev. 4, 6/16 en 7 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor functional overview high dynamic range mode of operation wh ere two images and taken using different exposures. these images are output in from the sensor and the isp must combine them into one high dynamic range image. figure 2: typical configuration: serial four-lane hispi interface notes: 1. all power supplies mu st be adequately decoupled. 2. on semiconductor recommends a resistor value of 1.5k ? , but a greater value may be used for slower two-wire speed. 3. the parallel interface output pads can be left unco nnected if the serial output interface is used. 4. on semiconductor recommends that 0.1 ? f and 10 ? f decoupling capacitors for each power supply are mounted as close as possible to the pad. actual values and results may vary depending on lay- out and design considerations. refer to the ar 0237 demo headboard schematics for circuit recom- mendations. 5. on semiconductor recommends that analog powe r planes are placed in a manner such that cou- pling with the digital power planes is minimized. 6. i/o signals voltage must be configured to match v dd _io voltage to minimize any leakage currents. v dd _io v dd _slvs v dd _pll v dd v aa v dd v aa v aa _pix master clock (6C48 mhz) s data sclk reset_bar test extclk d gnd a gnd digital ground analog ground digital core power 1 hispi power 1 analog power 1 to controller from controller v dd _io v dd _pll pll power 1 digital i/o power 1 1.5k : 2 1.5k : 2 analog power 1 v aa _pix slvsc_n slvsc_p slvs0_p slvs0_n slvs1_p slvs1_n slvs2_p slvs2_n slvs3_p slvs3_n v dd _slvs trigger oe_bar s addr shutter flash
ar0237cs/d rev. 4, 6/16 en 8 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor functional overview figure 3: typical configuration: parallel pixel data interface notes: 1. all power supplies mu st be adequately decoupled. 2. on semiconductor recommends a resistor value of 1.5k ? , but a greater value may be used for slower two-wire speed. 3. the serial interface output pads and v dd slvs can be left unconnected if the parallel output inter- face is used. 4. on semiconductor recommends that 0.1 ? f and 10 ? f decoupling capacitors for each power supply are mounted as close as possible to the pad. actual values and results may vary depending on lay- out and design considerations. refer to the ar 0237 demo headboard schematics for circuit recom- mendations. 5. on semiconductor recommends that analog powe r planes are placed in a manner such that cou- pling with the digital power planes is minimized. 6. i/o signals voltage must be configured to match v dd _io voltage to minimize any leakage currents. 7. the extclk input is limited to 6-48 mhz. v dd master clock (6-48 mhz) s data sclk test frame_valid d out [11:0] extclk d gnd digital ground analog ground digital core power 1 to controller from controller line_valid pixclk reset_bar v dd _io digital i/o power 1 1.5k 2 1.5k 2, v aa v aa _pix analog power 1 vdd_pll pll power 1 analog power 1 v aa _pix v dd _io v dd _pll v dd v aa trigger oe_bar a gnd s addr shutter flash
ar0237cs/d rev. 4, 6/16 en 9 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor functional overview figure 4: 80-ball ibga package a b c d e f g h j top view (ball down) slvs0_p slvs1_p slvsc_p slvs2_p slvs3_p v dd _pll slvs0_n slvs1_n slvsc_n slvs2_n slvs3_n extclk v dd _ slvs d gnd d gnd v dd d gnd s addr s clk s data a gnd d gnd v dd _io v aa _pix line_ valid frame_ valid pixclk flash d out 7 d out 1 d out 11 d out 10 d out 9 test d out 4d out 3 d out 6 d out 8 d gnd trigger oe_bar d out 0 d out 2 d out 5 reset_ bar 12 3 567 8 4 v dd d gnd shutter reserved 9 d gnd v aa v aa v aa v aa v dd v dd v dd v dd v dd reserved d gnd d gnd d gnd d gnd d gnd d gnd d gnd d gnd a gnd a gnd a gnd v dd _io v dd _io v dd _io v dd _io v dd _io a gnd d gnd d gnd v dd _io
ar0237cs/d rev. 4, 6/16 en 10 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor functional overview table 3: pin descriptions, 80-ball ibga name ibga pin type description slvs0_p a2 output hispi serial data, lane 0, differential p. slvs1_p a3 output hispi serial data, lane 1, differential p. slvsc_p a4 output hispi serial ddr clock differential p. slvs2_p a5 output hispi serial data, lane 2, differential p. slvs3_p a6 output hispi serial data, lane 3, differential p. v dd _pll b1 power pll power. slvs0_n b2 output hispi serial data, lane 0, differential n. slvs1_n b3 output hispi serial data, lane 1, differential n. slvsc_n b4 output hispi serial ddr clock differential n. slvs2_n b5 output hispi serial data, lane 2, differential n. slvs3_n b6 output hispi serial data, lane 3, differential n. shutter b9 output control for external mechanical shutte r. can be left floating if not used. v aa c1, g1, d9, f9 power analog power. a gnd c2, g2, d8, e8, f8 power analog ground. v dd _slvs c4 power slvs power v dd c5, j5, a9, h9, a7, d1, f1 power digital power. reserved c9, f7 d gnd b7, c7, d7, e7, g7, b8, c8, g8, d2, e2, f2, h2, c3, g3, h3, c6, j6 power digital ground. extclk d3 input external input clock. pixclk d4 output pixel clock out. dout is valid on rising edge of this clock. s addr d5 input two-wire serial address select. 0: 0x20. 1: 0x30 trigger d6 input exposure synchronization input. v aa _pix e9 power pixel power. v dd _io e1, h1, j2, j7, a8, g9, j9 power i/o supply power. s data e3 i/o two-wire serial data i/o. flash e4 output flash control output. frame_valid e5 output asserted when dout frame data is valid. s clk e6 input two-wire serial clock input. d out 11 f3 output parallel pixel data output (msb) d out 10 f4 output parallel pixel data output. d out 9f5 output parallel pixel data output. line_valid f6 output asserted when do ut line data is valid. d out 8g4 output parallel pixel data output. d out 7g5 output parallel pixel data output. d out 6g6 output parallel pixel data output. d out 5h4 output parallel pixel data output. d out 4h5 output parallel pixel data output. d out 3h6 output parallel pixel data output. reset_bar h7 input asynchronous reset (active low). all settings are rest ored to factory default. test h8 input. manufacturing test enable pin (connect to dgnd).
ar0237cs/d rev. 4, 6/16 en 11 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor functional overview figure 5: 48 pin mplcc package hispi d out 2j1 output parallel pixel data output. d out 1j3 output parallel pixel data output. d out 0j4 output parallel pixel data output (lsb) oe_bar j8 input output enable (active low). table 3: pin descriptions, 80-ball ibga name ibga pin type description
ar0237cs/d rev. 4, 6/16 en 12 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor functional overview table 4: mplcc hispi pin out pin name type description 1 slvscn output hispi serial ddr clock differential n 2 slvs1p output hispi serial data, lane 1, differential p 3 slvs1n output hispi serial data, lane 1, differential n 4 slvs0p output hispi serial data, lane 0, differential p 5 slvs0n output hispi serial data, lane 0, differential n 6 vdd_slvs power slvs power 0.3 v-0.6 v 7 dgnd power digital ground 8 vdd_pll power pll power 9 extclk input external input clock 10 vaa power analog power 11 agnd power analog ground 12 vdd_io power i/o power supply 13 vdd power digital power 14 dgnd power digital ground 15 reserved 16 vaa power analog power 17 agnd power analog ground 18 dgnd power digital ground 19 vdd power digital power 20 vdd_io power i/o power supply 21 flash output flash control output 22 test input manufacturing test enable pin (connect to dgng) 23 sdata i/o two-wire serial data i/o 24 saddr input two-wire serial address select. 0: 0x20, 1: 0x30 25 sclk input two-wire serial clock input 26 reset_bar input asynchronous reset (active low). all settings are restored to factory default 27 oe_bar input output enable (active low) 28 trigger input exposure synchronization input 29 shutter output control for external mechanica l shutter. can be left floating if not used. 30 vdd_io power i/o power supply 31 vdd power digital power 32 dgnd power digital ground 33 agnd power analog ground 34 vaa_pix power pixel power 35 vaa power analog power 36 reserved 37 vaa power analog power 38 vaa_pix power pixel power 39 agnd power analog ground
ar0237cs/d rev. 4, 6/16 en 13 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor functional overview 40 dgnd power digital ground 41 vdd power digital power 42 vdd_io power i/o power supply 43 vdd 1v8_phy power 1.8 v supply for hivcm mode 44 slsv3p output hispi serial data, lane 3, differential p 45 slvs3n output hispi serial data, lane 3, differential n 46 slvs2p output hispi serial data, lane 2, differential p 47 slvs2n output hispi serial data, lane 2, differential n 48 slvslcp output hispi serial ddr clock differential p table 4: mplcc hispi pin out
ar0237cs/d rev. 4, 6/16 en 14 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor functional overview figure 6: 48 pin mplcc package parallel table 5: mplcc parallel pin out pin name type description 1 dout6 output data output 6 2 dout7 output data output 7 3 dout8 output data output 8 4 dout9 output data output 9 5 dout10 output data output 10 6 dout11 power data output 11 7 dgnd power digital ground 8 vdd_pll power pll power 9 extclk input external input clock 10 vaa power analog power 11 agnd power analog ground 12 vdd_io power i/o power supply 13 vdd power digital power 14 dgnd power digital ground 15 reserved 16 vaa power analog power 17 agnd power analog ground 18 vdd power digital power 19 vdd_io power i/o power supply 20 flash power flash control output 21 pixclk output pixel clock 22 frame_valid output frame valid 23 test input manufacturing test enable pin (connect to dgng) 24 dgnd power digital ground
ar0237cs/d rev. 4, 6/16 en 15 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor functional overview 25 sdata i/o two-wire serial data i/o 26 line_valid output line valid 27 saddr input two-wire serial address select. 0: 0x20, 1: 0x30 28 sclk input two-wire serial clock input 29 vdd_io power i/o power supply 30 vdd power digital power 31 reset_bar input asynchronous reset (active low). all settings are restor ed to factory default 32 oe_bar input output enable (active low) 33 trigger input exposure synchronization input 34 shutter output control for external mechanical s hutter. can be left floating if not used. 35 reserved input reserved 36 agnd power analog ground 37 vaa_2v8 power analog power 38 vaa_pix power pixel power 39 agnd power analog ground 40 dgnd power digital ground 41 vdd power digital power 42 vdd_io power i/o power supply 43 dout0 output data output 0 44 dout1 output data output 1 45 dout2 output data output 2 46 dout3 output data output 3 47 dout4 output data output 4 48 dout5 output data output 5 table 5: mplcc parallel pin out
ar0237cs/d rev. 4, 6/16 en 16 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor pixel data format pixel data format pixel array structure while the sensor's format is 1928 x1088, addi tional active columns and active rows are included for use when horizontal or vertic al mirrored readout is enabled, to allow readout to start on the same pixel. the pixe l adjustment is always performed for mono- chrome or color versions. the active area is surrounded with optically transparent dummy pixels to improve image uniformity wi thin the active area. not all dummy pixels or barrier pixels can be read out. figure 7: pixel array description 10 b arr i er + 4 b or d er p i xe l s light dummy pixel active pixel 10 barrier + 4 border pixels 1944 2 barrier + 6 border pixels 2 barrier + 6 border pixels 1116 1928 1 x 1088 5.78 mm x 3.26 mm
ar0237cs/d rev. 4, 6/16 en 17 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor pixel data format figure 8: pixel color pattern detail (rgb) (top right corner) figure 9: pixel color pattern detail rgb ir (top right corner) active pixel (0,0) array pixel (0, 0) row reado ut direction g b g b g b r g r g r g r g r g r g r g r g r g r g r g r g g b g b g b g b g b g b g b g b g b column readout direction active pixel (0,0) array pixel (0, 0) row reado ut direction g ir g ir b g r g r g b g b g r g r g b g g ir g ir g ir g ir g ir g ir column readout direction
ar0237cs/d rev. 4, 6/16 en 18 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor pixel data format default readout order by convention, the sensor core pixel array is shown with pixel (0,0) in the top right corner (see figure 8). this reflects the actual layout of the array on the die. also, the first pixel data read out of the sensor in de fault condition is that of pixel (10, 14). when the sensor is imaging, the active surface of the sensor faces the scene as shown in figure 10. when the image is read out of the sensor, it is read one row at a time, with the rows and columns sequenced as shown in figure 10. figure 10: imaging a scene lens pixel (0,0) row readout order column readout order scene sensor (rear view)
ar0237cs/d rev. 4, 6/16 en 19 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor features overview features overview for a complete description, recommendations, and usage guidelines for product features, refer to the ar0237 developer guide. 3.0 ? m dual conversion gain pixel to improve the low light performance and keep the high dynamic range, a large (3.0um) dual conversion gain pixel is implemented for better image optimization. with a dual conversion gain pixel, the conversion gain of the pixel may be dynamically changed to better adapt the pixel response based on dynamic range of the scene. hdr by default, the sensor powers up in line ar mode. one can change to hdr mode. the hdr scheme used is multi-exposure hdr. this allows the sensor to handle up to 96 db of dynamic range. in hdr mode, the sensor sequentially captures two exposures by maintaining two separate read and reset pointe rs that are interleaved within the rolling shutter readout. the exposure ratio may be set to 4x, 8x, 16x, or 32x. sensor also provides flexibility to choose any exposure ratio by setting number of t2 exposure rows indepen- dent of the t1 exposure. the data will be output as line interleaved data as described in the t1/t2 line interleaved mode section. ther e is also an option to output either t1 only or t2 only. resolution the active array supports a maximum of 192 8x1088 pixels to support 1080p resolution. utilizing a 3.0um pixel will result in an op tical format of 1/2.7-inch (approximately 6.6mm diagonal). frame rate at full (1080p) resolution, the ar0237 is capabl e of running up to 60 fps in linear mode and 30 fps in line interleaved mode. image acquisition mode the ar0237 supports two image acquisition modes: ? electronic rolling shutter (ers) mode this is the normal mode of operation. when the ar0237 is streaming, it generates frames at a fixed rate, and each frame is integrated (exposed) using the ers. when ers mode is in use, timing and control logic with in the sensor sequences through the rows of the array, resetting and then re ading each row in turn. in the time interval between reset- ting a row and subsequently reading that row, the pixels in the row integrate incident light. the integration (exposur e) time is controlled by varying the time between row reset and row readout. for each row in a frame, the time between row reset and row readout is the same, leading to a uniform in tegration time across the frame. when the integration time is changed (by using the two- wire serial interface to change register settings), the timing and control logic controls the transition from old to new integration time in such a way that the stream of outp ut frames from the ar0237 switches cleanly from the old integration time to the new whil e only generating frames with uniform inte- gration. see ?changes to integration time? in the ar0237 register reference.
ar0237cs/d rev. 4, 6/16 en 20 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor features overview ? global reset mode. this mode can be used to acquire a single im age at the current resolution. in this mode, the end point of the pixel integration time is controlled by an external electromechanical shutter, and the ar0237 provides control signal s to interface to that shutter. the benefit of using an external electromechanical shutter is that it eliminates the visual artifacts associated with ers operation. visual artifacts arise in ers op eration, particularly at low frame rates, because an ers image effectively integrates each row of the pixel array at a different point in time. embedded data and statistics the ar0237 has the capability to output imag e data and statistics embedded within the frame timing. there are two types of information embedded within the frame readout. ? embedded data: if enabled, these are displayed on the two rows immediately before the first active pixel row is displayed. ?embedded statistics: if enabled, these are displayed on the two ro ws immediately after the last active pixel row is displayed. multi-camera synchronization the ar0237 supports advanced line synchroniz ation controls for multi-camera (stereo) support. slave mode the slave mode feature of the ar0237 supports triggering the star t of a frame readout from an input signal that is supplied from an external asic. the slave mode signal allows for precise control of frame rate and register change updates. context switching and register updates the user has the option of using the highly configurable context memory, or a simplified implementation in which only a subset of registers is available for switching. the ar0237 supports a highly configurable contex t switching ram of size 256 x 16. within this context memory, changes to any register may be stored. the register set for each context must be the same, but the number of contexts and registers per context are limited only by the size of the context memory. alternatively, the user may switch between two predefined register sets a and b by writing to a context switch change bit. when the context switch is configured to context a the sensor will reference the context a regist ers. if the context switch is changed from a to b during the readout of frame n, the sensor will then reference the context b coarse_integration_time registers in frame n+ 1 and all other context b registers at the beginning of reading frame n+2. the sensor will show the same behavior when changing from context b to context a. the registers listed in table 6 are context-switchable:
ar0237cs/d rev. 4, 6/16 en 21 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor features overview table 6: list of configurable registers for context a and context b analog/digital gains a programmable analog gain of 1.0x to 16x (linear and hdr) applie d simultaneously to all color channels will be featured along with a digital gain of 1x to 16x that may be configured on a per color channel basis. note that with the rgb ir sensor digital gain should only be applied to all color channels equally since with the 4x4 kernel the gains will not be applied to the proper color channe l. analog gain can be applied per exposure in line interleaved mode. skipping/binning modes the ar0237 supports subsampling. subsampling allows the sensor to read out a smaller set of active pixels by either skipping, binning, or summing pixels within the readout window. horizontal binning is achieved in the digital readout. the sensor will sample the combined 2x adjacent pixels within the same color plane. vertical row binning is applied in the pixel readout. row binning can be configured as 2x rows within the same color plane. pixel skipping can be configured up to 2x in both the x-direction and y- context a context b register description register description coarse_integration_time coarse_integration_time_cb line_length_pck line_length_pck_cb frame_length_lines frame_length_lines_cb row_bin row_bin_cb col_bin col_bin_cb fine_gain fine_gain_cb coarse_gain coarse_gain_cb coarse_integration_time2 co arse_integration_time2_cb dcg_manual_set dcg_manual_set_cb dcg_manual_set_t1 dcg_manual_set_t1_cb bypass_pix_comb bypass_pix_cb coarse_gain_t1 coarse_gain_t1_cb fine_gain_t1 fine_gain_t1_cb x_addr_start x_addr_start_cb y_addr_start y_addr_start_cb x_addr_end x_addr_end_cb y_addr_end y_addr_end_cb y_odd_inc y_odd_inc_cb x_odd_inc x _odd_inc_cb green1_gain green1_gain_cb blue_gain blue_gain_cb red_gain red_gain_cb green2_gain green2_gain_cb global_gain global_gain_cb operation_mode_ctrl ope ration_mode_ctrl_cb bypass_pix_comb bypass_pix_comb_cb
ar0237cs/d rev. 4, 6/16 en 22 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor features overview direction. skipping pixels in the x-direction will not reduce the row time. skipping pixels in the y direction will reduce the number of rows from the sensor e ffectively reducing the frame time. skipping will introduce image artifacts from aliasing. the ar0237 supports row wise vertical binni ng. row wise vertical summing is only supported in monochrome sensors. binning and summing is not su pported with rgb ir sensors. clocking options the sensor contains a phase-locked loop (pll ) that is used for timing generation and control. the required vco clock frequency is attained through the use of a pre-pll clock divider followed by a multiplier. the pll multip lier should be an even integer. if an odd integer (m) is programmed, the pll will default to the lower (m-1) value to maintain an even multiplier value. the multiplier is followed by a set of dividers used to generate the output clocks required for the sensor array, the pixel analog and digital readout paths, and the output parallel and serial interfaces . use of the pll is required when using the hispi interface. temperature sensor the ar0237 sensor has a built-in ptat-based temperature sensor, accessible through registers, that is capable of measuring die ju nction temperature. the value read out from the temperature sensor register is an adc output value that needs to be converted downstream to a final temperature value in degrees celsius. since the ptat device char- acteristic response is quite linear in the temperature range of operation required, a simple linear function can be used to conv ert the adc output value to the final tempera- ture in degrees celsius. a single reference point will be made available via register read as well as a slope for back-calculating the junction temperature value. an error of +/-5% or better over the full specified operating range of th e sensor is to be expected. silicon / firmware / sequ encer revision information a revision register will be provided to read out (via i 2 c) silicon and sequencer/otpm revision information. this will be helpful to distinguish among different lots of material if there are future otpm or sequencer revisions. lens shading correction the latest lens shading correction algorithm will be included for potential low z height applications. compression when the ar0237 is configured for linear mode operation, the se nsor can optionally compress 12-bit data to 10-bit using a-law compression. the a-law compression is disabled by default. packaging the ar0237 will be offered in a 10x10 80 -ibga package (parallel and hispi) and a 11.43x1143 48 pin mplcc (hisspi) package.
ar0237cs/d rev. 4, 6/16 en 23 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor features overview parallel interface the parallel pixel data interface uses these output-only signals: ?frame_valid ?line_valid ?pixclk ?d out [11:0] the parallel pixel data interface is disabled by default at power up and after reset. it can be enabled by programming r0x301a. when the parallel pixel data interface is in use, the serial data output signals can be left unconnected. high speed serial pix el (hispi) interface the hispi interface supports three protocols, streaming-s, streamin g-sp, and packetized sp. the streaming protocols conform to a stan dard video application where each line of active or intra-frame blanking provided by th e sensor is transmitted at the same length. the packetized sp protocol will transmit only the active data ignoring line-to-line and frame-to-frame blanking data. the hispi interface building block is a unidirectional differential serial interface with four data and one double data rate (ddr) cl ock lanes. one clock for every four serial data lanes is provided for phase alignment across multiple lanes. the ar0237 supports serial data widths of 10 or 12 bits on one, two, or four lanes. the specification includes a dll to compensate for differences in group delay for each data lane. the dll is connected to the clock lane and each data lane, which acts as a control master for the output delay buffers. once the dll has gained phase lock, each lane can be delayed in 1/8 unit interval (ui) steps. this additional delay allows the user to increase the setup or hold time at the receiver circuits and can be used to compensate for skew introduced in pcb design. delay compensation may be set for clock and/or data lines in the hispi_timing register r0x31c0. if the dll ti ming adjustment is not required, the data and clock lane delay settings should be set to a default code of 0x0000 to reduce jitter, skew, and power dissipation. sensor control interface the two-wire serial interface bus enables read/write access to control and status regis- ters within the ar0237. the interface protoc ol uses a master/slave model in which a master controls one or more slave devices. the sensor acts as a slave device. the master generates a clock (s clk ) that is an input to the sensor and is used to synchronize trans- fers. data is transferred between the master an d the slave on a bidirectional signal (s data ). s data is pulled up to v dd _io off-chip by a 1.5k ? resistor. either the slave or master device can drive s data low-the interface protocol determines which device is allowed to drive s data at any given time. the tw o-wire serial interface ca n run at 100 khz or 400 khz. t1/t2 line interleaved mode the ar0237 outputs the t1 and t2 exposures separately, in a line interleaved format. the purpose of this is to enable off chip hdr linear combination and processing. see the ar0237 developer guide for more information.
ar0237cs/d rev. 4, 6/16 en 24 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor features overview figure 11: quantum efficiency - rgb 0 10 20 30 40 50 60 70 80 350 450 550 650 750 850 950 1050 1150 quantum efficiency (%) wavelength (nm) red green blue
ar0237cs/d rev. 4, 6/16 en 25 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor features overview figure 12: quantum efficiency - rgb - ir 0 10 20 30 40 50 60 70 0 200 400 600 800 1000 1200 quantum efficiency (%) wavelength (nm) red (%) green (r) (%) green (b) (%) blue (%) ir (%)
ar0237cs/d rev. 4, 6/16 en 26 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor electrical specifications electrical specifications unless otherwise stated, the following specifications apply under the following condi- tions: v dd = 1.8v ? 0.10/+0.15; v dd _io = v dd _pll = v aa = v aa _pix = 2.8v 0.3v; v dd _slvs = 0.4v ? 0.1/+0.2; t a = -30 c to +85 c-40 c to +105 c; output load = 10pf; frequency = 74.25 mhz; hispi off. two-wire serial register interface the electrical characterist ics of the two-wire serial register interface (s clk , s data ) are shown in figure 13 and table 7. figure 13: two-wire serial bus timing parameters note: read sequence: for an 8-bit read, read wa veforms start after write command and register address are issued. table 7: two-wire serial bus characteristics f extclk = 27 mhz; v dd = 1.8v; v dd _io = 2.8v; v aa = 2.8v; v aa _pix = 2.8v; v dd _pll = 2.8v; t a = 25c parameter symbol standard mode fast mode unit min max min max s clk clock frequency f scl 0 100 0 400 khz hold time (repeate d) start condition. after this period, the first clock pulse is generated t hd;sta 4.0 - 0.6 - ? s low period of the sclk clock t low 4.7 - 1.3 - ? s high period of the sclk clock t high 4.0 - 0.6 - ? s set-up time for a repeated start condition t su;sta 4.7 - 0.6 - ? s data hold time t hd;dat 0 4 3.45 5 0 6 0.9 5 ? s data set-up time t su;dat 250 - 100 6 -ns rise time of both s data and s clk signals t r - 1000 20 + 0.1cb 7 300 ns fall time of both s data and s clk signals t f - 300 20 + 0.1cb 7 300 ns set-up time for stop condition t su;sto 4.0 - 0.6 - ? s bus free time between a stop and start condition t buf 4.7 - 1.3 - ? s capacitive load for each bus line cb - 400 - 400 pf s sr t su;sto t su;sta t hd;sta t high t low t su;dat t hd;dat t f s data s clk p s t buf t r t f t r t hd;sta
ar0237cs/d rev. 4, 6/16 en 27 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor electrical specifications notes: 1. this table is based on i 2 c standard (v2.1 january 20 00). philips semiconductor. 2. two-wire control is i 2 c-compatible. 3. all values referred to v ihmin = 0.9 v dd and v ilmax = 0.1v dd levels. sensor exclk = 27 mhz. 4. a device must internally provide a ho ld time of at least 300 ns for the s data signal to bridge the undefined region of the falling edge of s clk . 5. the maximum t hd;dat has only to be met if the devi ce does not stretch the low period ( t low) of the s clk signal. 6. a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t su;dat 250 ns must then be me t. this will automatically be the ca se if the device does not stretch the low period of the s clk signal. if such a device does stretch the low period of the s clk signal, it must output the next data bit to the s data line t r max + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specificatio n) before the s clk line is released. 7. cb = total capacitance of one bus line in pf. i/o timing by default, the ar0237 launches pixel data, fv, and lv with the falling edge of pixclk. the expectation is that the user captures d out [11:0], fv, and lv using the rising edge of pixclk. see figure 14 below and table 8 on page 28 for i/o timing (ac) characteristics. figure 14: i/o timing diagram serial interface input pin capacitance cin_si - 3.3 - 3.3 pf s data max load capacitance cload_sd - 30 - 30 pf s data pull-up resistor rsd 1.5 4.7 1.5 4.7 k ? table 7: two-wire serial bu s characteristics (continued) f extclk = 27 mhz; v dd = 1.8v; v dd _io = 2.8v; v aa = 2.8v; v aa _pix = 2.8v; v dd _pll = 2.8v; t a = 25c parameter symbol standard mode fast mode unit min max min max data[11:0] line_valid/ pixclk extclk t r t extclk t f frame_valid leads line_valid by 6 pixclks. frame_valid trails line_valid by 6 pixclks. t plh t pfh t pfl t pll t pd pxl _0 pxl _1 pxl _2 pxl _n 90% 10% t rp t fp 90% 10% frame_valid
ar0237cs/d rev. 4, 6/16 en 28 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor electrical specifications note: i/o timing characteristics are me asured under the following conditions: - temperature is 25c ambient - 10 pf load - 1.8v i/o supply voltage table 8: i/o timing characteristics symbol definition condition min typ max unit f extclk1s input clock frequency 6 C 48 mhz t extclk1 input clock period 20.8 C 166 ns t r input clock rise time C 3 C ns t f input clock fall time C 3 C ns t rp pixclk rise time 2 3.5 5 ns t fp pixclk fall time 2 3.5 5 ns clock duty cycle 45 50 55 % t cp extclk to pixclk propagation delay nominal voltages, pll disabled 10 14 18 ns f pixclk pixclk frequency default, nominal voltages 6C74.25mhz t pd pixclk to data valid default, nominal voltages C3C ns t pfh pixclk to fv high default, nominal voltages C3C ns t plh pixclk to lv high default, nominal voltages C3C ns t pfl pixclk to fv low default, nominal voltages C3C ns t pll pixclk to lv low default, nominal voltages C3C ns c load output load capacitance C <10 C pf c in input pin capacitance C 2.5 C pf
ar0237cs/d rev. 4, 6/16 en 29 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor electrical specifications dc electrical characteristics the dc electrical characteristics are shown in the tables below. caution stresses greater than those listed in table 10 may cause permanent damage to the device. this is a stress rating only, and functional ope ration of the device at these or any other con- ditions above those indicated in the operational sections of this specification is not implied. note: exposure to ab solute maximum rating conditions for extended periods may affect reliability. table 9: dc electrical characteristics symbol definition condition min typ max unit v dd core digital voltage 1.7 1.8 1.95 v v dd _io i/o digital voltage 1.7/2.5 1.8/2.8 1.9/3.1 v v aa analog voltage 2.5 2.8 3.1 v v aa _pix pixel supply voltage 2.5 2.8 3.1 v v dd _pll pll supply voltage 2.5 2.8 3.1 v v dd _slvs hispi supply voltage 0.3 0.4 0.6 v v ih input high voltage v dd _io*0.7 C C v v il input low voltage C C v dd _io*0.3 v i in input leakage current no pull-up resistor; v in = v dd _io or d gnd 20 C C ? a v oh output high voltage v dd _io-0.3 C C v v ol output low voltage C C 0.4 v i oh output high current at specified v oh -22 C C ma i ol output low current at specified v ol CC22ma table 10: absolute maximum ratings symbol definition condition min max unit v dd _max core digital voltage C0.3 2.4 v v dd _io_max i/o digital voltage C0.3 4 v v aa _max analog voltage C0.3 4 v v aa _pix pixel supply voltage C0.3 4 v v dd _pll pll supply voltage C0.3 4 v vdd_slvs_max hispi i/o digital voltage C0.3 2.4 v t st storage temperature C40 85 c
ar0237cs/d rev. 4, 6/16 en 30 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor electrical specifications note: operating currents are measured in ma at the following conditions: - v aa = v aa _pix = v dd _pll = v dd _io =2.8 v - v dd = 1.8 v - pll enabled and pixclk = 74.25 mhz - low power mode enabled - t a = 25c note: operating currents are measured in ma at the following conditions: - v aa = v aa _pix = v dd _pll =2.8 v - v dd = v dd _io= 1.8 v - pll enabled and pixclk = 74.25 mhz - low power mode enabled - t a = 25c dark image, 8x analog ga in, hcg, 20ms integration time table 11: 1080p30 linear 74 mhz parallel 2.8v definition condition symbol voltage min typ max unit digital operating current streaming 1080p30 idd 1.8 20 34 50 ma i/o digital operating current streaming 1080p30 idd_io 2.8 15 28 50 ma analog operating current streaming 1080p30 iaa 2.8 15 26 50 ma pixel supply current streaming 1080p30 iaa_pix 2.8 1 3 7 ma pll supply current streaming 1080p30 idd_pll 2.8 5.5 6.4 7 ma power 138.2 238.72 409.2 mw table 12: 1080p30 linear 74 mhz parallel 1.8v definition condition symbol voltage min typ max unit digital operating current streaming 1080p30 idd 1.8 20 34 50 ma i/o digital operating current streaming 1080p30 idd_io 1.8 10 14 30 ma analog operating current streaming 1080p30 iaa 2.8 15 26 50 ma pixel supply current streaming 1080p30 iaa_pix 2.8 1 3 7 ma pll supply current streaming 1080p30 idd_pll 2.8 5.5 6.4 7 ma power 114.2 185.52 323.2 mw
ar0237cs/d rev. 4, 6/16 en 31 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor electrical specifications note: operating currents are measured in ma at the following conditions: - v aa = v aa _pix = v dd _pll =2.8 v - v dd = v dd _io= 1.8 v - v dd _slvs= 0.4v - pll enabled and pixclk = 74.25 mhz - 4-lane hispi mode - low power mode enabled - t a = 25c dark image, 8x analog gain , hcg, 20ms integration time note: operating currents are measured in ma at the following conditions: - v aa = v aa _pix = v dd _pll =2.8 v - v dd = v dd _io = v dd _slvs= 1.8 v - pll enabled and pixclk = 74.25 mhz - 4-lane hispi mode - low power mode enabled - t a = 25c dark image, 8x analog gain , hcg, 20ms integration time table 13: 1080p30 linear 74 mhz hispi slvs definition condition symbol voltage min typ max unit digital operating current streaming 1080p30 idd 1.8 25 44 65 ma analog operating current streaming 1080p30 iaa 2.8 15 26 50 ma pixel supply current streaming 1080p30 iaa_pix 2.8 1 3 7 ma pll supply current streaming 1080p30 idd_pll 2.8 6 7.5 8.5 ma slvs supply current streaming 1080p30 idd_slvs 0.4 6 9.5 14 ma power 109 185.2 306 mw table 14: 1080p30 linear 74 mhz hispi hivcm definition condition symbol voltage min typ max unit digital operating current streaming 1080p30 idd 1.8 25 44 65 ma analog operating current streaming 1080p30 iaa 2.8 15 26 50 ma pixel supply current streaming 1080p30 iaa_pix 2.8 1 3 7 ma pll supply current streaming 1080p30 idd_pll 2.8 6 7.5 8.5 ma slvs supply current streaming 1080p30 idd_slvs 1.8 12 20 35 ma power 128.2 217.4 363.4 mw
ar0237cs/d rev. 4, 6/16 en 32 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor electrical specifications note: operating currents are measured in ma at the following conditions: - v aa = v aa _pix = v dd _pll =2.8 v - v dd = v dd _io= 1.8 v - v dd _slvs= 0.4v - pll enabled and pixclk = 74.25 mhz - 4-lane hispi mode - t a = 25c dark image, 8x analog gain, hcg, 20ms integration time note: operating currents are measured in ma at the following conditions: - v aa = v aa _pix = v dd _pll = 2.8 v - v dd = v dd _io = 1.8 v - v dd _slvs = 1.8 v - pll enabled and pixclk = 74.25 mhz - 4-lane hispi mode - t a = 25c dark image, 8x analog ga in, hcg, 20ms integration time hispi electrical specifications the on semiconductor ar0237 sensor suppor ts both slvs and hivcm hispi modes. refer to the high-speed seri al pixel (hispi) interface ph ysical layer specification v2.00.00 for electrical definitions, specif ications, and timing information. the v dd _slvs supply in this datasheet corresponds to v dd _tx in the hispi physical layer specifica- tion. similarly, v dd is equivalent to v dd _hispi as referenced in the specification. the dll as implemented on ar0237 is limited in the number of available delay steps and differs from the hispi specification as described in this section. table 15: 1080p30 74 mhz line interleaved slvs definition condition symbol voltage min typ max unit digital operating current streaming 1080p30 idd 1.8 50 88 130 ma analog operating current streaming 1080p30 iaa 2.8 20 36 60 ma pixel supply current streaming 1080p30 iaa_pix 2.8 1 4 8 ma pll supply current streaming 1080p30 idd_pll 2.8 7 8.5 9.5 ma slvs supply current streaming 1080p30 idd_slvs 0.4 6 9.5 14 ma power 170.8 298 442.6 mw table 16: 1080p30 74 mhz line interleaved hivcm definition condition symbol voltage min typ max unit digital operating current streaming 1080p30 idd 1.8 50 88 130 ma analog operating current streaming 1080p30 iaa 2.8 20 36 60 ma pixel supply current streaming 1080p30 iaa_pix 2.8 1 4 8 ma pll supply current streaming 1080p30 idd_pll 2.8 7 8.5 9.5 ma slvs supply current streaming 1080p30 idd_slvs 1.8 12 20 35 ma power 190 330.2 500 mw table 17: channel skew measurement conditions: v dd _hispi = 1.8v;v dd _hispi_tx = 0.4v; data rate =480 mbps; dll set to 0 data lane skew in reference to clock tchskew1phy -150 ps
ar0237cs/d rev. 4, 6/16 en 33 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor power-on reset and standby timing power-on reset and standby timing power-up sequence the recommended power-up sequence for the ar0237 is shown in figure 15. the avail- able power supplies (v dd _io, v dd , v dd _slvs, v dd _pll, v aa , v aa _pix) must have the separation specified below. 1. turn on v dd _pll power supply. 2. after 100 ? s, turn on v aa and v aa _pix power supply. 3. after 100 ? s, turn on v dd _io power supply. 4. after 100 ? s, turn on vdd power supply. 5. after 100 ? s, turn on vdd_slvs power supply. 6. after the last power supply is stable, enable extclk. 7. assert reset_bar for at least 1ms. the parall el interface will be tri-stated during this time. 8. wait 150000 extclks (for internal initialization into software standby. 9. configure pll, output, and imag e settings to desired values. 10. wait 1ms for the pll to lock. 11. set streaming mode (r0x301a[2] = 1). figure 15: power up v dd _pll (2.8) v aa _pix v aa (2.8) v dd _io (1.8/2.8) v dd (1.8) v dd _slvs (0.4) extclk reset_bar t0 t1 t2 t3 tx t4 t5 t6 hard reset internal initialization software standby pll lock streaming
ar0237cs/d rev. 4, 6/16 en 34 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor power-on reset and standby timing notes: 1. xtal settling time is component-de pendent, usually taking about 10 C 100 ms. 2. hard reset time is the minimum time required af ter power rails are settled. in a circuit where hard reset is held down by rc circuit, then the rc ti me must include the all power rail settle time and xtal settle time. 3. it is critical that v dd _pll is not powered up after the other power supplies. it must be powered before or at least at the same time as the others. if the case happens that v dd _pll is powered after other supplies then sensor may have functionality is sues and will experience high current draw on this supply. table 18: power-up sequence definition symbol minimum typical maximum unit v dd _pll to v aa /v aa _pix 3 t0 0 100 C ? s v aa /v aa _pix to v dd _io t1 0 100 C ? s v dd _io to v dd t2 0 100 C ? s v dd to v dd _slvs t3 0 100 C ? s xtal settle time tx C 30 1 Cms hard reset t4 1 2 CC ms internal initializat ion t5 150000 C C extclks pll lock time t6 1 C C ms
ar0237cs/d rev. 4, 6/16 en 35 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor power-on reset and standby timing power-down sequence the recommended power-down sequence for the ar0237 is shown in figure 16. the available power supplies (v dd _io, v dd , v dd _slvs, v dd _pll, v aa , v aa _pix) must have the separation specified below. 1. disable streaming if output is active by setting standby r0x301a[2] = 0 2. the soft standby state is re ached after the current row or frame, depending on config- uration, has ended. 3. turn off v dd _slvs. 4. turn off v dd . 5. turn off v dd _io. 6. turn off v aa /v aa _pix. 7. turn off v dd _pll. figure 16: power down t4 is required between power down and next power up time; all decoupling caps from regulators must be completely discharged. table 19: power-down sequence definition symbol minimum typical maximum unit v dd _slvs to v dd t0 0 C C ? s v dd to v dd _io t1 0 C C ? s v dd _io to v aa /v aa _pix t2 0 C C ? s v aa /v aa _pix to v dd _pll t3 0 C C ? s power down until next power up time t4 100 C C ms v dd _io (1.8/2.8) t4 t 0 t1 t3 t2 extclk v dd _slvs (0.4) v dd (1.8) v aa _pix v aa (2.8) v dd _pll (2.8) power down until next power up cycle
ar0237cs/d rev. 4, 6/16 en 36 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor power-on reset and standby timing package diagrams figure 17: plcc 48 11.43 x 11.43 package diagram (case 776aq) plcc48 11.43x11.43 case 776aq issue a date 20 nov 201 5
ar0237cs/d rev. 4, 6/16 en 37 ?semiconductor components industries, llc, 2016. ar0237cs: 1/2.7-inch 2.1 mp/full hd digital image sensor power-on reset and standby timing figure 18: 80ibga 10x10 package diagram (case 503ba) ibga80 10x10 case 503ba issue o date 07 jul 201 5
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